The GPIOs of Apollo1 and Apollo2 series MCUs can be configured via a MUX for up to 8 different functionalities.
Following schematic can be found in the datasheet in the chapter GPIO and Pad Configuration Module (Apollo1: chapter 6, Apollo2: chapter 7):
Block diagram for the General Purpose I/O (GPIO) Module
The IO-cell itself can be configured in a complex way. The datasheet is showing the following PAD schematic:
Pad Connection Details
The default configuration is GPIO and the state of all GPIOs is by default not connected to the PAD. Only for GPIO20 and GPIO21 the input is selected and the function SWD (debugging) is activated.
Reading GPIOs
PADKEY
Before a GPIO can be read, the input of it must be enabled. Therefore first of all the registers must be unlocked by writing 0x73 into the PADKEY register of the GPIO peripheral:
GPIO->PADKEY = 0x00000073;
Now the PADREGn and CFGm register of the GPIO peripheral must be touched.
PADREGn
The PADREGn registers are named from PADREGA up to PADREGM. The PAD configuration in PADREGn consists of 8 bits, so in each PADREGn register are stored 4 PAD configurations.
- PADxPULL (x = 0…49) is used to enable the pullup.
- PADxINPEN (x = 0…49) is used to enable the PAD input.
- PADxSTRNG (x = 0…49) is used to set the drive strength to low strength or high strength
- PADxFNCSEL (x = 0…49) is a 3 bit field defining the function. 0x3 is the GPIO function
- For GPIOs with lower-side switch capability, PADxPWERDN can be used to enable this feature
- For GPIOs with higher-side switch capability, PADxPWERUP can be used to enable this feature
- For GPIOs with I2C capability the 2 bit field PADxRSEL can select pullups of 1.5K, 6K, 12K and 24K.
To read the GPIO, PADxINPEN must be set. For GPIO0 this must be:
GPIO->PADREGA_b.PAD0INPEN = 1;
CFGm
The CFGm registers are named from CFGA up to CFGG. The PAD configuration in CFGm consists of 4 bits, so in each CFGm register are stored 8 PAD configurations.
- GPIOxINCFG is configuring the input behaviour. To avoid floating, the internal logic is returning 0 if not set, otherwise the read the GPIO pin data.
- GPIOxOUTCFG is a 2 bit field setting the output to: Disabled, Push-Pull, Open-Drain or Tri-State.
- GPIOxINTD is setting the interrupt behaviour to rising-edge or falling-edge
The GPIO usage must be set, in this example for GPIO0:
GPIO->PADREGA_b.PAD0FNCSEL = 0x3;
To enable the input on PAD GPIO0, following line is needed, otherwise only “0” is read.
GPIO->CFGA_b.GPIO0INCFG = 0;
PADKEY
Now the PADKEY register can be locked again:
GPIO->PADKEY = 0x00000000;
RDA / RDB
Now the RDA or RDB register can be used to read out the GPIO. RDA is for GPIO0..31 and RDB for GPIO32..49.
if (GPIO->RDA & (1 << 0))
{
//GPIO0 is high
}
else
{
//GPIO0 is low
}
Writing GPIOs
PADKEY
Before a GPIO can be written, the output of it must be enabled. Therefore first of all the registers must be unlocked by writing 0x73 into the PADKEY register of the GPIO peripheral:
GPIO->PADKEY = 0x00000073;
Now the PADREGn and CFGm register of the GPIO peripheral must be touched.
PADREGn
The PADREGn registers are named from PADREGA up to PADREGM. The PAD configuration in PADREGn consists of 8 bits, so in each PADREGn register are stored 4 PAD configurations.
- PADxPULL (x = 0…49) is used to enable the pullup.
- PADxINPEN (x = 0…49) is used to enable the PAD input.
- PADxSTRNG (x = 0…49) is used to set the drive strength to low strength or high strength
- PADxFNCSEL (x = 0…49) is a 3 bit field defining the function. 0x3 is the GPIO function
- For GPIOs with lower-side switch capability, PADxPWERDN can be used to enable this feature
- For GPIOs with higher-side switch capability, PADxPWERUP can be used to enable this feature
- For GPIOs with I2C capability the 2 bit field PADxRSEL can select pullups of 1.5K, 6K, 12K and 24K.
The GPIO usage must be set, in this example for GPIO1:
GPIO->PADREGA_b.PAD1FNCSEL = 0x3;
CFGm
The CFGm registers are named from CFGA up to CFGG. The PAD configuration in CFGm consists of 4 bits, so in each CFGm register are stored 8 PAD configurations.
- GPIOxINCFG is configuring the input behaviour. To avoid floating, the internal logic is returning 0 if not set, otherwise the read the GPIO pin data.
- GPIOxOUTCFG is a 2 bit field setting the output to: Disabled, Push-Pull, Open-Drain or Tri-State.
- GPIOxINTD is setting the interrupt behaviour to rising-edge or falling-edge
To enable the output on PAD GPIO1, following line is needed:
GPIO->CFGA_b.GPIO1OUTCFG = 1; //using push-pull
PADKEY
Now the PADKEY register can be locked again:
GPIO->PADKEY = 0x00000000;
WTA / WTB / WTSA / WTSB / WTCA / WTCB
The WTA register can be used to access the GPIO0..31 and the WTB regsiter to access the GPIO32..49. Example for GPIO1:
GPIO->WTA |= (1 << 1); //set GPIO1 to high
GPIO->WTA &= ~(1 << 1); //set GPIO1 to low
Unfortunately these instructions having the need of read-modify-write. To set and clear bits more easily, the WTS<A/B> and WTC<A/B> registers can be used. The WT<set/clear><A/B> registers are used to set or clear bits. Example for GPIO1:
GPIO->WTSA = (1 << 1); //set GPIO1 to high
GPIO->WTCA = (1 << 1); //set GPIO1 to low
Tristate GPIOs: ENA / ENB / ENSA / ENSB / ENCA / ENCB
Accordingly for TriState configuration the EN<A/B> and EN<set/clear><A/B> registers can be used to control the output.
Run the code
The complete example is workable with MCU Templates for Apoll1 and Apollo2 from FEEU http://www.fujitsu.com/feeu or by contacting FEEU directly info.feeu@de.fujitsu.com
See also MCU Templates
Hardware Availability
The Apollo1 and Apollo2 MCUs and EVKs are available at the webshop of Fujitsu Electronics Europe GmbH (FEEU):
